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tp3056b monolithic serial interface combined pcm codec and filter slws072a may 1998 revised august 1998 1 post office box 655303 ? dallas, texas 75265 complete pcm codec and filtering systems include: transmit high-pass and low-pass filtering receive low-pass filter with (sin x)/x correction active rc noise filters m -law and a-law compatible coder and decoder internal precision voltage reference serial i/o interface internal autozero circuitry m -law/a-law operation pin-selectable 5 -v operation low operating power . . . 60 mw typ power-down mode ...5 mw typ automatic power down ttl- or cmos-compatible digital interface maximizes line interface card circuit density description the tp3056b monolithic serial interface combined pcm codec and filter device is comprised of a single-chip pcm codec (pulse code-modulated encoder and decoder) and analog filters. this device provides all the functions required to interface a full-duplex (2-wire) voice telephone circuit with a tdm (time-division-multiplexed) system. primary applications include: ? line interface for digital transmission and switching of t1/e1 carrier, pabx, and central office telephone systems ? subscriber line concentrators ? digital-encryption systems ? digital voice-band data-storage systems ? digital signal processing the tp3056b is designed to perform the transmit encoding (a/d conversion) and receive decoding (d/a conversion), and the appropriate filtering of analog signals in a pcm system. this device is intended to be used at the analog termination of a pcm line or trunk. it requires a master clock of 2.048 mhz, a transmit/receive data clock that is synchronous with the master clock (but can vary from 64 khz to 2.048 mhz), and transmit and receive frame-sync pulses. the tp3056b contains patented circuitry to achieve low transmit channel idle noise and is not recommended for applications in which the composite signals on the transmit side are below 55 dbm0. this device, available in 16-pin n pdip (plastic dual-in-line package) and 16-pin dw soic (small outline ic) packages, is characterized for operation from 0 c to 70 c. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foa m during storage or handling to prevent electrostatic damage to the mos gates. copyright ? 1998, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v bb anlg gnd vfro v cc fsr dr asel pdn vfxi + vfxi gsx tsx fsx dx bclk mclk dw or n package (top view)
tp3056b monolithic serial interface combined pcm codec and filter slws072a may 1998 revised august 1998 2 post office box 655303 ? dallas, texas 75265 functional block diagram gsx 14 v bb anlg gnd v cc 412 5 v fsx 5 v 9 8 10 7 12 5 mclk pdn bclk asel fsr tsx 13 power amplifier timing and control dr 6 clk receive regulator s/h dac rc active filter 11 dx oe transmit regulator voltage reference s/h dac switched- capacitor band-pass filter rc active filter 3 vfro + vfxi + 16 15 vfxi analog input switched- capacitor low-pass filter analog output digital output digital input
tp3056b monolithic serial interface combined pcm codec and filter slws072a may 1998 revised august 1998 3 post office box 655303 ? dallas, texas 75265 terminal functions terminal i/o description name no. i/o description anlg gnd 2 analog ground. all signals are referenced to anlg gnd. asel 7 i a-law/ m -law select. when asel is connected to v cc , a-law is selected. when asel is connected to gnd or v bb , m -law is selected. bclk 10 i transmit/receive bit clock. bclk shifts pcm data out on dx during transmit and shifts pcm data in through dr during receive. bclk can vary from 64 khz to 2.048 mhz, but must be synchronous with mclk. dr 6 i receive data input. pcm data is shifted into dr at the trailing edge of the bclk following the fsr leading edge. dx 11 o dx is the 3-state pcm data output that is enabled by fsx. data is shifted out on the rising edge of bclk. fsr 5 i receive-frame sync pulse input. fsr enables bclk to shift pcm data in dr. fsr is an 8-khz pulse train (see figures 1 and 2 for timing details). fsx 12 i transmit-frame sync pulse. fsx enables bclk to shift out the pcm data on dx. fsx is an 8-khz pulse train (see figures 1 and 2 for timing details). gsx 14 o analog output of the transmit input amplifier. gsx is used to set gain externally. mclk 9 i transmit/receive master clock. mclk must be 2.048 mhz. pdn 8 i power down. when pdn is connected high, the device is powered down. when pdn is connected low or left floating, the device is powered up. pdn is internally tied low. tsx 13 o transmit channel time-slot strobe. tsx is an open-drain output that pulses low during the encoder time slot. v bb 1 negative power supply. v bb = 5 v 5% v cc 4 positive power supply. v cc = 5 v 5% vfro 3 o analog output of the receive channel power amplifier vfxi + 16 i noninverting input of the transmit input amplifier vfxi 15 i inverting input of the transmit input amplifier
tp3056b monolithic serial interface combined pcm codec and filter slws072a may 1998 revised august 1998 4 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)2 supply voltage, v cc (see note 1) 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage, v bb (see note 1) 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range at any analog input or output v cc + 0.3 v to v bb 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range at any digital input or output v cc + 0.3 v to anlg gnd 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . continuous total dissipation see dissipation rating table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range: tp3056b 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: dw or n package 260 c . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltages are with respect to gnd. dissipation rating table package t a 25 c power rating derating factor above t a = 25 c t a = 70 c power rating t a = 85 c power rating dw 1025 mw 8.2 mw/ c 656 mw 533 mw n 1150 mw 9.2 mw/ c 736 mw 598 mw recommended operating conditions (see note 2) min nom max unit supply voltage, v cc 4.75 5 5.25 v supply voltage, v bb 4.75 5 5.25 v high-level input voltage, v ih 2.2 v low-level input voltage, v il 0.6 v common-mode input voltage range, v icr 3 2.5 v load resistance, gsx, r l 10 k w load capacitance, gsx, c l 50 pf operating free-air temperature, t a 0 70 c 3 measured with cmrr > 60 db note 2: to avoid possible damage to these cmos devices and resulting reliability problems, the power-up procedure described in t he device power-up sequence paragraphs later in this document should be followed. electrical characteristics over recommended ranges of supply voltage operating free-air temperature range, in a-law and m -law modes (unless otherwise noted) supply current parameter test conditions tp3056b unit parameter test conditions min typ max unit i cc su pp ly current from v cc power down no load 0.5 1 ma i cc s u ppl y c u rrent from v cc operating no load 6 9 ma i bb su pp ly current from v bb power down no load 0.5 1 ma i bb s u ppl y c u rrent from v bb operating no load 6 9 ma all typical values are at v cc = 5 v, v bb = 5 v, and t a = 25 c.
tp3056b monolithic serial interface combined pcm codec and filter slws072a may 1998 revised august 1998 5 post office box 655303 ? dallas, texas 75265 electrical characteristics at v cc = 5 v 5%, v bb = 5 v 5%, gnd at 0 v, t a = 25 c (unless otherwise noted) digital interface parameter test conditions min max unit v oh high-level output voltage dx i h = - 3.2 ma 2.4 v v ol low level out p ut voltage dx i l = 3.2 ma 0.4 v v ol lo w- le v el o u tp u t v oltage tsx i l = 3.2 ma, drain open 0.4 v i ih high-level input current v i = v ih to v cc 10 m a i il low-level input current all digital inputs v i = gnd to v il 10 m a i oz output current in high-impedance state dx v o = gnd to v cc 10 m a analog interface with transmit amplifier input parameter test conditions min typ 2 max unit v icr 3 common-mode input voltage range 2.5 v i i input current vfxi + or vfxi v i = 2.5 v to 2.5 v 200 na r i input resistance vfxi + or vfxi v i = 2.5 v to 2.5 v 10 m w a v open-loop voltage amplification vfxi + to gsx 5000 b i unity-gain bandwidth gsx 1 2 mhz v io input offset voltage vfxi + or vfxi 20 mv cmrr common-mode rejection ratio 60 db k svr supply-voltage rejection ratio 60 db 2 all typical values are at v cc = 5 v, v bb = 5 v, and t a = 25 c. 3 measured with cmrr > 60 db. analog interface with receive amplifier output parameter test conditions min typ 2 max unit receive output drive voltage r l = 10 k w 2.5 v output resistance vfro 1 3 w load resistance vfro = 2.5 v 600 w load capacitance vfro to gnd 500 pf output dc offset voltage vfro to gnd 200 mv 2 all typical values are at v cc = 5 v, v bb = 5 v, and t a = 25 c.
tp3056b monolithic serial interface combined pcm codec and filter slws072a may 1998 revised august 1998 6 post office box 655303 ? dallas, texas 75265 operating characteristics, over operating free-air temperature range, v cc = 5 v 5%, v bb = 5 v 5%, gnd at 0 v, v i = 1.2276 v, f = 1.02 khz, transmit input amplifier connected for unity gain, noninverting, in a-law and m -law modes, (unless otherwise noted) filter gains and tracking errors parameter test conditions min typ 2 max unit maximum peak transmit m -law 3.17 dbm0 2.501 v overload level a-law 3.14 dbm0 2.492 v transmit filter gain, absolute 3 (at 0 dbm0) t a = 25 c 0.15 0.15 db 3 f = 16 hz 40 3 f = 50 hz 30 3 f = 60 hz 26 3 f = 200 hz 1.8 0.1 transmit filter gain relative to absolute 3 f = 300 hz to 3000 hz 0.15 0.15 db transmit filter gain , relative to absolute 3 f = 3300 hz 0.35 0.05 db f = 3400 hz 0.8 0 f = 4000 hz 14 f 4600 hz (measure response from 0 hz to 4000 hz) 32 absolute 3 transmit gain variation with temperature and supply voltage relative to absolute transmit gain 0.1 0.1 db 3 dbm0 input level 40 dbm0 0.2 transmit gain tracking error with level sinusoidal test method, reference level = 10 dbm0 40 dbm0 > input level 50 dbm0 0.4 db 50 dbm0 > input level 55 dbm0 0.8 receive filter gain, absolute 3 (at 0 dbm0) input is digital code sequence for 0-dbm0 signal, t a = 25 c 0.15 0.15 db 3 f = 0 hz to 3000 hz, t a = 25 c 0.15 0.15 receive filter gain relative to absolute 3 f = 3300 hz 0.35 0.05 db recei v e filter gain , relati v e to absol u te 3 f = 3400 hz 0.8 0 db f = 4000 hz 14 absolute 3 receive gain variation with temperature and supply voltage t a = full range, see note 3 0.1 0.1 db sinusoidal test method; 3 dbm0 input level 40 dbm0 0.2 receive gain tracking error with level reference input pcm code corresponds to an ideally 40 dbm0 > input level 50 dbm0 0.4 db encoded 10 dbm0 signal 50 dbm0 > input level 55 dbm0 0.8 pseudo-noise test method; 3 dbm0 input level 40 dbm0 0.25 transmit and receive gain tracking error with level (a-law, ccitt g 712) pseudo noise test method reference input pcm code corresponds to an ideally 40 dbm0 > input level 50 dbm0 0.3 db encoded 10 dbm0 signal 50 dbm0 > input level 55 dbm0 0.45 2 all typical values are at v cc = 5 v, v bb = 5 v, and t a = 25 c. 3 absolute rms signal levels are defined as follows: v i = 1.2276 v = 0 dbm0 = 4 dbm at f = 1.02 khz with r l = 600 w . note 3: full range for the tp3056b is 0 c to 70 c.
tp3056b monolithic serial interface combined pcm codec and filter slws072a may 1998 revised august 1998 7 post office box 655303 ? dallas, texas 75265 operating characteristics, over operating free-air temperature range, v cc = 5 v 5%, v bb = 5 v 5%, gnd at 0 v, v i = 1.2276 v, f = 1.02 khz, transmit input amplifier connected for unity gain, noninverting, in a-law and m -law modes, (unless otherwise noted) (continued) envelope delay distortion with frequency parameter test conditions min typ 2 max unit transmit delay, absolute (at 0 dbm0) f = 1600 hz 290 315 m s 3 f = 500 hz to 600 hz 195 220 3 f = 600 hz to 800 hz 120 145 3 f = 800 hz to 1000 hz 50 75 transmit delay, relative to absolute 3 f = 1000 hz to 1600 hz 20 40 m s f = 1600 hz to 2600 hz 55 75 f = 2600 hz to 2800 hz 80 105 f = 2800 hz to 3000 hz 130 155 receive delay, absolute (at 0 dbm0) f = 1600 hz 180 200 m s 3 f = 500 hz to 1000 hz 40 25 3 f = 1000 hz to 1600 hz 30 20 receive delay, relative to absolute 3 f = 1600 hz to 2600 hz 70 90 m s f = 2600 hz to 2800 hz 100 125 f = 2800 hz to 3000 hz 140 175 2 all typical values are at v cc = 5 v, v bb = 5 v, and t a = 25 c. 3 absolute rms signal levels are defined as follows: v i = 1.2276 v = 0 dbm0 = 4 dbm at f = 1.02 khz with r l = 600 w . noise parameter test conditions min typ 2 max unit transmit noise, c-message weighted m -law vfxi = 0 v 9 14 dbrnc0 transmit noise, psophometric weighted (see note 4) a-law vfxi = 0 v 78 75 dbm0p receive noise, c-message weighted m -law pcm code equals alternating positive and negative zero. 2 4 dbrnc0 receive noise, psophometric weighted a-law pcm code equals positive zero. 86 83 dbm0p noise, single frequency vfxi+ = 0 v, f = 0 khz to 100 khz, loop-around measurement 53 dbm0 2 all typical values are at v cc = 5 v, v bb = 5 v, and t a = 25 c. note 4: measured by extrapolation from the distortion test result. this parameter is achieved through use of patented circuitry and is not recommended for applications in which the composite signals on the transmit side are below 55 dbm0. crosstalk parameter test conditions min typ 2 max unit crosstalk, transmit to receive f = 300 hz to 3000 hz, dr at steady pcm code 90 75 db crosstalk, receive to transmit (see note 5) vfxi = 0 v, f = 300 hz to 3000 hz 90 75 db 2 all typical values are at v cc = 5 v, v bb = 5 v, and t a = 25 c. note 5: receive-to-transmit crosstalk is measured with a 50 dbm0 activation signal applied at vfxi +. power amplifiers parameter test conditions min max unit m i 0 db 0 l l f b tt th 0 1 db li it bl dl dr td r l = 600 w 1.65 maximum 0 dbm0 rms level for better than 0.1 db linearity over the range if 10 dbm0 to 3 dbm0 balanced load,r l , connected between vfro and gnd r l = 1200 w 1.75 v over the range if 10 dbm0 to 3 dbm0 between vfro and gnd r l = 30 k w 2 v rms signal/distortion r l = 600 w 50 db
tp3056b monolithic serial interface combined pcm codec and filter slws072a may 1998 revised august 1998 8 post office box 655303 ? dallas, texas 75265 operating characteristics, over operating free-air temperature range, v cc = 5 v 5%, v bb = 5 v 5%, gnd at 0 v, v i = 1.2276 v, f = 1.02 khz, transmit input amplifier connected for unity gain, noninverting, in a-law and m -law modes, (unless otherwise noted) (continued) power supply rejection parameter test conditions min max unit v 5 v 100 v f=0hzto4khz a-law 38 db positive power-supply rejection, transmit v cc = 5 v + 100 mvrms, vfxi+ = 50 dbm0 f = 0 h z to 4 kh z m -law 38 dbc 2 vfxi+ = 50 dbm0 f = 4 khz to 50 khz 40 db v 5 v 100 v f=0hzto4khz a-law 35 db negative power-supply rejection, transmit v bb = 5 v + 100 mvrms, vfxi+ = 50 dbm0 f = 0 h z to 4 kh z m -law 35 dbc 2 vfxi+ = 50 dbm0 f = 4 khz to 50 khz 40 db pcm d l iti f=0hzto4khz a-law 40 db positive power-supply rejection, receive pcm code equals positive zero, v cc =5v+100mvrms f = 0 h z to 4 kh z m -law 40 dbc 2 v cc = 5 v + 100 mvrms f = 4 khz to 50 khz 40 db pcm d l iti f=0hzto4khz a-law 38 db negative power-supply rejection, receive pcm code equals positive zero, v bb = 5 v + 100 mvrms f = 0 h z to 4 kh z m -law 38 dbc 2 v bb = 5 v + 100 mvrms f = 4 khz to 50 khz 40 db s 0 dbm0, 300-hz to 3400-hz input applied to dr (measure individual image signals at vfro) 30 db spurious out-of-band signals at the channel out p ut (vfro) f = 4600 hz to 7600 hz 33 channel output (vfro) f = 7600 hz to 8400 hz 40 db f = 8400 hz to 100 khz 40 2 the unit dbc applies to c-message weighting.
tp3056b monolithic serial interface combined pcm codec and filter slws072a may 1998 revised august 1998 9 post office box 655303 ? dallas, texas 75265 operating characteristics, over operating free-air temperature range, v cc = 5 v 5%, v bb = 5 v 5%, gnd at 0 v, v i = 1.2276 v, f = 1.02 khz, transmit input amplifier connected for unity gain, noninverting, in a-law and m -law modes, (unless otherwise noted) (continued) distortion parameter test conditions min max unit 3 level = 3 dbm0 33 2 3 level = 0 dbm0 to - 30 dbm0 36 2 signal to distortion ratio transmit or receive half channel 3 level = 40 dbm0 transmit 29 dbc 2 si gna l - t o- di s t or ti on ra ti o, t ransm it or rece i ve h a lf -c h anne l 3 le v el = 40 dbm0 receive 30 dbc 2 level = 55 dbm0 transmit 14 le v el = 55 dbm0 receive 15 single-frequency distortion products, transmit 46 db single-frequency distortion products, receive 46 db intermodulation distortion loop-around measurement, vfxi + = 4 dbm0 to 21 dbm0, two frequencies in the range of 300 hz to 3400 hz 41 db level = 3 dbm0 33 si l di i i i h lf h l (a l ) level = 6 dbm0 to 27 dbm0 36 signal-to-distortion ratio, transmit half-channel (a-law) (ccitt g 714) level = 34 dbm0 33.5 db (ccitt g . 714) level = 40 dbm0 28.5 level = 55 dbm0 13.5 level = 3 dbm0 33 si l t di t ti ti i h lf h l (a l ) level = 6 dbm0 to 27 dbm0 36 signal-to-distortion ratio, receive half-channel (a-law) (ccitt g 714) level = 34 dbm0 34.2 db (ccitt g . 714) level = 40 dbm0 30 level = 55 dbm0 15 2 the unit dbc applies to c-message weighting. 3 sinusoidal test method (see note 6) pseudo-noise test method note 6: m -law measurements are made using a c-message weighted filter, and a-law measurements are made using a psophometric weighted filter.
tp3056b monolithic serial interface combined pcm codec and filter slws072a may 1998 revised august 1998 10 post office box 655303 ? dallas, texas 75265 timing requirements over recommended ranges of operating conditions (see figures 1 and 2) min nom max unit f clock(m) frequency of master clock mclk 2.048 mhz f clock(b) frequency of bit clock, transmit bclk 64 2048 khz t w1 pulse duration, mclk high 160 ns t w2 pulse duration, mclk low 160 ns t r1 rise time of master clock (20% to 80%) mclk 50 ns t f1 fall time of master clock (80% to 20%) mclk 50 ns t r2 rise time of bit clock (20% to 80%), transmit bclk 50 ns t f2 fall time of bit clock (80% to 20%), transmit bclk 50 ns t su1 setup time, bclk high (and fsx in long-frame sync mode) before mclk (first bit clock after the leading edge of fsx) 100 ns t w3 pulse duration, bclk high, v ih = 2.2 v 160 ns t w4 pulse duration, bclk low, v il = 0.6 v 160 ns t h1 hold time, fsx or fsr low after bclk low (long frame only) 0 ns t h2 hold time, bclk high after fsx or fsr (short frame only) 0 ns t su2 setup time, fsx or fsr high before bclk (long frame only) 80 ns t su3 setup time, dr valid before bclk 50 ns t h3 hold time, dr valid after bclk 50 ns t su4 setup time, fsx or fsr high before bclk , short-frame sync pulse (1 or 2 bit-clock periods long) (see note 7) 50 ns t h4 hold time, fsx or fsr high after bclk , short-frame sync pulse (1 or 2 bit-clock periods long) (see note 7) 100 ns t h5 hold time, fsx or fsr high after bclk , long-frame sync pulse (from 3 to 8 bit-clock periods long) 100 ns t w5 minimum pulse duration of fsx or fsr (frame sync pulse e low level), 64-kbps operating mode 160 ns note 7: for short-frame sync timing, fsr and fsx must go high while their respective bit clocks are high. switching characteristics over recommended ranges of operating conditions (see figures 1 and 2) parameter test conditions min max unit t d1 delay time, bclk high to data valid at dx load = 150 pf plus 2 lsttl loads 2 0 140 ns t d2 delay time, bclk high to tsx low load = 150 pf plus 2 lsttl loads 2 140 ns t d3 delay time, bclk (or 8 clock fsx in long frame only) low to data output (dx) disabled 50 165 ns t d4 delay time, fsx or bclk high to data valid at dx (long frame only) c l = 0 pf to 150 pf 20 165 ns 2 nominal input value for an lsttl load is 18 k w .
tp3056b monolithic serial interface combined pcm codec and filter slws072a may 1998 revised august 1998 11 post office box 655303 ? dallas, texas 75265 parameter measurement information 1 8 7 6 5 4 3 2 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 t h2 t h4 t su4 t h3 t h3 t su3 8 7 6 5 4 3 2 1 bclk fsr dr fsx dx t d3 t d1 t h4 t su4 t h2 bclk mclk t w1 t su1 f clock(m) t w2 t f1 t r1 t d3 t d2 tsx 80% 20% 80% 20% 20% 80% 20% 80% 20% 80% 20% 80% 80% 20% 80% 20% 80% 20% 80% 20% 80% 20% 20% 80% figure 1. short frame sync timing
tp3056b monolithic serial interface combined pcm codec and filter slws072a may 1998 revised august 1998 12 post office box 655303 ? dallas, texas 75265 parameter measurement information t h3 t h3 t su3 t h5 t su2 t h1 t d3 t d3 t d1 t d4 t d4 dr fsr bclk dx fsx 9 8 7 6 5 4 3 2 1 t h5 f clock(b) t su2 t h1 bclk t w4 t w3 t f2 t r2 t su1 t su1 mclk t w2 f clock(m) t f1 t w1 t r1 78 6 5 4 3 2 1 123456 8 7 20% 80% 80% 20% 80% 20% 80% 80% 20% 80% 20% 20% 80% 20% 20% 20% 80% 80% 20% 20% 80% 20% 80% 20% 80% 80% t w4 t w3 80% figure 2. long frame sync timing
tp3056b monolithic serial interface combined pcm codec and filter slws072a may 1998 revised august 1998 13 post office box 655303 ? dallas, texas 75265 principles of operation system reliability and design considerations tp3056b system reliability and design considerations are described in the following paragraphs. latch-up latch-up is possible in all cmos devices. it is caused by the firing of a parasitic scr that is present due to the inherent nature of cmos. when a latch-up occurs, the device draws excessive amounts of current and will continue to draw heavy current until power is removed. latch-up can result in permanent damage to the device if supply current to the device is not limited. even though the tp3056b is heavily protected against latch-up, it is still possible to cause latch-up under certain conditions in which excess current is forced into or out of one or more terminals. latch-up can occur when the positive supply voltage drops momentarily below ground, when the negative supply voltage rises momentarily above ground, or possibly if a signal is applied to a terminal after power has been applied but before the ground is connected. this can happen if the device is hot-inserted into a card with the power applied, or if the device is mounted on a card that has an edge connector and the card is hot-inserted into a system with the power on. to help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased schottky diode with a forward voltage drop of less than or equal to 0.4 v (1n5711 or equivalent) between the power supply and gnd (see figure 3). if it is possible that a tp3056b-equipped card that has an edge connector could be hot-inserted into a powered-up system, it is also important to ensure that the ground edge connector traces are longer than the power and signal traces so that the card ground is always the first to make contact. v cc dgnd v bb figure 3. latch-up protection diode connection
tp3056b monolithic serial interface combined pcm codec and filter slws072a may 1998 revised august 1998 14 post office box 655303 ? dallas, texas 75265 principles of operation system reliability and design considerations (continued) device power-up sequence latch-up also can occur if a signal source is connected without the device being properly grounded. a signal applied to one terminal could then find a ground through another signal terminal on the device. to ensure proper operation of the device and as a safeguard against this sort of latch-up, it is recommended that the following power-up sequence always be used: 1. ensure that no signals are applied to the device before the power-up sequence is complete. 2. connect gnd. 3. apply v bb (most negative voltage). 4. apply v cc (most positive voltage). 5. force a power down condition in the device. 6. connect clocks. 7. release the power down condition. 8. apply fs synchronization pulses. 9. apply the signal inputs. when powering down the device, this procedure should be followed in the reverse order. internal sequencing power-on reset circuitry initializes the tp3056b device when power is first applied, placing it in the power-down mode. the dx and vfro outputs go into the high-impedance state and all nonessential circuitry is disabled. a low level applied to the pdn terminal powers up the device and activates all internal circuits. the 3-state pcm data output, dx, remains in the high-impedance state until the arrival of the second fsx pulse. general operation a 2.048-mhz clock signal applied to mclk serves as the master clock for both the receive and the transmit directions. bclk must have a bit clock signal applied to it, which then serves as the bit clock for both the receive and the transmit directions. bclk can be in the range from 64 khz to 2.048 mhz, but must be synchronous with mclk. the encoding cycle begins with each fsx pulse, and the pcm data from the previous cycle is shifted out of the enabled dx output on the rising edge of bclk. after eight bit-clock periods, the 3-state dx output is returned to the high-impedance state. with an fsr pulse, pcm data is latched in via dr on the falling edge of bclk. fsx and fsr must be synchronous with mclk.
tp3056b monolithic serial interface combined pcm codec and filter slws072a may 1998 revised august 1998 15 post office box 655303 ? dallas, texas 75265 principles of operation short-frame sync operation the device can operate with either a short-frame sync pulse or a long-frame sync pulse. on power up, the device automatically goes into the short-frame mode where both fsx and fsr must be one bit-clock period long with timing relationships specified in figure 1. with fsx high during a falling edge of bclk, the next rising edge of bclk enables the 3-state output buffer, outputting the sign bit at dx. the remaining seven bits are shifted out on the following seven rising edges, with the next falling edge disabling dx. with fsr high during a falling edge of bclk, the next falling edge of bclk latches in the sign bit. the following seven falling edges latch in the seven remaining bits. long-frame sync operation both fsx and fsr must be three or more bit-clock periods long to use the long-frame sync mode with timing relationships as shown in figure 2. using the transmit frame sync (fsx), the device determines whether a short- or long-frame sync pulse is being used. for 64-khz operation, the frame-sync pulse must be kept low for a minimum of 160 ns. the rising edge of fsx or bclk, whichever occurs later, enables the 3-state output buffer, outputting the sign bit at dx. the next seven rising edges of bclk shift out the remaining seven bits. the falling edge of bclk following the eighth rising edge, or fsx going low, whichever occurs later, disables dx. a rising edge on fsr, the receive-frame sync pulse, causes the pcm data at dr to be latched in on the next eight falling edges of bclk. transmit section the transmit section consists of an input amplifier, filters, and an encoding adc. the input is an operational amplifier with provision for gain adjustment using two external resistors. the low-noise and wide-bandwidth characteristics of these devices provide gains in excess of 20 db across the audio passband. the operational amplifier drives a unity-gain filter consisting of an rc active prefilter followed by an eighth-order switched-capacitor band-pass filter clocked at 256 khz. the output of this filter is routed to the encoder sample-and-hold circuit. the adc is a compressing type and converts the analog signal to pcm data in accordance with m -law or a-law coding conventions, as selected. a precision voltage reference provides a nominal input overload voltage of 2.5 v peak. the sampling of the filter output is controlled by the fsx frame-sync pulse; then the successive-approximation encoding cycle begins. the resulting 8-bit code is loaded into a buffer and shifted out through dx at the next fsx pulse. the total encoding delay is approximately 290 m s. any offset voltage due to the filters or comparator is cancelled by sign-bit integration. receive section the receive section is unity gain and consists of an expanding dac, filters, and a power amplifier. decoding is m -law or a-law (as selected by the asel terminal), and the decoded analog output signal is routed to the input of a fifth-order switched-capacitor low-pass filter. this filter is clocked at 256 khz and corrects for the (sin x)/x attenuation caused by the 8-khz sample/hold of the dac. next is a second-order rc active post-filter/power amplifier capable of driving an external 600- w load. when fsr goes high, the data at dr is stepped in on the falling edge of the next eight bclk clocks. at the end of the decoder time slot, the decoding cycle begins and 10 m s later, the decoder dac output is updated. the decoder delay is about 10 m s (decoder update) plus 110 m s (filter delay) plus 62.5 m s (1/2 frame), or a total of approximately 180 m s.
tp3056b monolithic serial interface combined pcm codec and filter slws072a may 1998 revised august 1998 16 post office box 655303 ? dallas, texas 75265 application information power supplies while the terminals of the tp3056b device is well protected against electrical misuse, it is recommended that the standard cmos practice be followed, ensuring that ground is connected to the device before any other connections are made. in applications where the printed-circuit board can be plugged into a hot socket with power and clocks already present, an extra long ground pin in the connector should be used. all ground connections to each device should meet at a common point as close as possible to the device anlg gnd terminal. this minimizes the interaction of ground return currents flowing through a common bus impedance. v cc and v bb supplies should be decoupled by connecting 0.1- m f decoupling capacitors to this common point. these bypass capacitors must be connected as close as possible to the device v cc and v bb terminals. for best performance, the ground point of each codec/filter on a card should be connected to a common card ground in star formation rather than via a ground bus. this common ground point should be decoupled to v cc and v bb with 10- m f capacitors. figure 4 shows a typical tp3056b application. (2.048 mhz) data out digital interface analog interface r2 r1 from slic (analog in) pdn 5 v, gnd, or 5 v data in to slic (analog out) 5 v 0.1 m f 0.1 m f 5 v mclk bclk dx fsx gsx vfxi vfxi+ pdn asel dr fsr vfro v cc anlg gnd v bb note a: transmit gain = 20 log 1 2 4 3 5 6 7 8 16 15 14 12 11 10 9 tp3056b r1 r2 r2 , ( r1 r2 ) 10 k tsx 13 figure 4. typical synchronous application
tp3056b monolithic serial interface combined pcm codec and filter slws072a may 1998 revised august 1998 17 post office box 655303 ? dallas, texas 75265 mechanical data dw (r-pdso-g**) plastic small-outline package 16 pin shown 4040000 / b 03/95 seating plane 0.400 (10,15) 0.419 (10,65) 0.104 (2,65) max 1 0.012 (0,30) 0.004 (0,10) a 8 16 0.020 (0,51) 0.014 (0,35) 0.293 (7,45) 0.299 (7,59) 9 0.010 (0,25) 0.050 (1,27) 0.016 (0,40) (15,24) (15,49) pins ** 0.010 (0,25) nom a max dim a min gage plane 20 0.500 (12,70) (12,95) 0.510 (10,16) (10,41) 0.400 0.410 16 0.600 24 0.610 (17,78) 28 0.700 (18,03) 0.710 0.004 (0,10) m 0.010 (0,25) 0.050 (1,27) 0 8 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). d. falls within jedec ms-013
tp3056b monolithic serial interface combined pcm codec and filter slws072a may 1998 revised august 1998 18 post office box 655303 ? dallas, texas 75265 mechanical data n (r-pdip-t**) plastic dual-in-line package 20 0.975 (24,77) 0.940 (23,88) 18 0.920 0.850 14 0.775 0.745 (19,69) (18,92) 16 0.775 (19,69) (18,92) 0.745 a min dim a max pins ** 0.310 (7,87) 0.290 (7,37) (23.37) (21.59) seating plane 0.010 (0,25) nom 14/18 pin only 4040049/c 08/95 9 8 0.070 (1,78) max a 0.035 (0,89) max 0.020 (0,51) min 16 1 0.015 (0,38) 0.021 (0,53) 0.200 (5,08) max 0.125 (3,18) min 0.240 (6,10) 0.260 (6,60) m 0.010 (0,25) 0.100 (2,54) 0 15 16 pin shown notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms-001 (20 pin package is shorter then ms-001.)
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1998, texas instruments incorporated

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